A synchronization monitor design in dynamic heterogeneous redundancy architecture

Dynamic heterogeneous redundancy (DHR) is an architecture proposed to bolster the reliability and security of computer systems. In DHR, the synchronization challenges caused by the heterogeneity of the executors are very significant. These challenges are the primary cause of false positives in system arbitration. With more systems adopting DHR, research on synchronization issues has become crucial. A DHR system is modeled based on the application states and identify internal events as a key factor causing asynchronization. On this basis, a synchronization monitor (DHRSM) is designed to convert uncertain internal events into deterministic external events. This approach enables control over the application state transitions of the executors. DHRSM and two other synchronization methods are implemented on a DHR MCU and conduct experiments to evaluate their efficiency, overhead, and latency. The results show that DHRSM achieves the best comprehensive performance across different densities of internal and external events.