An Improved Graph Isomorphism Network Model for Analog Integrated Circuit Placement Performance Prediction

In the design of analog integrated circuits (ICs), the placement stage in layout design plays a crucial role in deter-mining the final circuit performance. Current automated placement algorithms are primarily driven by geometric constraints, often requiring repetitive iterations to optimize circuit performance. Accelerating the design process necessitates accurate evaluation of placement quality; however, the complex relationship between circuit perfor-mance and layout makes rapid and precise assessment challenging. Traditional methods for evaluating placement quality require the completion of the entire layout design, involving time-consuming processes such as DRC (De-sign Rule Checking), LVS (Layout Versus Schematic), parasitic parameter extraction, and simulation. The original Graph Isomorphism Network (GIN) model’s neglect of edge features and reliance on static aggregation mecha-nisms lead to incomplete topology-physics representations and degraded accuracy in predicting performance met-rics. To address the issues, we introduce a Modified Graph Isomorphism Network (MGIN) that utilizes edge fea-ture concatenation and adaptive weighted loss adjustment for multitask regression. MGIN effectively predicts multiple post-layout performance metrics using carefully crafted placement features. In comparison to baseline models, it achieves lower average relative error rates for operational transconductance amplifier circuits. Our re-sults demonstrate an average root mean square error (RMSE) of 3.549 and a relative error rate of 3.549% across multiple performance metrics. Our model achieves superior prediction accuracy over GIN, with an 80.4% lower average error. By mapping layout configurations directly to post-layout performance, the proposed MGIN offers specific and actionable guidance for iterative redesign in analog IC development.