A Reconfigurable Hardware Architecture for Packet Processing

In this paper, we propose a reconfigurable packet processing hardware architecture for future switch, in which several protocol-independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture, any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost, the processor cost model and optimization algorithm are proposed. The NetFPGA-based implementation shows a throughput of 94Gb/s with 64-B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.